Japanese Patent Application No. 2000-320978, filed Oct. 20, 2000 is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor device which retains data by refreshing, a method of refreshing the semiconductor device, a memory system, and an electronic instrument.
A virtually static RAM (VSRAM) is one type of semiconductor memory. Although memory cells of the VSRAM are the same as memory cells of a DRAM, the VSRAM does not need multiplexing of the column address and the row address. Moreover, the user can use the VSRAM without taking refreshing into consideration (transparency of refreshing).
A certain type of VSRAM is operated in two or more operating states such as a normal operating state and a power saving state. In such a VSRAM, sufficient consideration is not given to internal refreshing performed in each operating state. This problem is not limited to the VSRAM, but is common to dynamic type semiconductor memory devices equipped with a built-in refresh timer and refresh control sections.
The present invention has been achieved to overcome the above conventional problem. An object of the present invention is to provide technology capable of performing refresh operations suitable for two or more operating states of a semiconductor memory device.
(1) A first aspect of the present invention provides a method of refreshing a semiconductor device including a memory cell array divided into a plurality of blocks, the method comprising:
a first step of making the semiconductor device externally accessible,
a second step of refreshing a block other than a block to be externally accessed among the plurality of blocks of the memory cell array in a first refresh cycle when the semiconductor device is in an externally accessible state;
a third step of making the semiconductor device externally inaccessible; and
a fourth step of refreshing each of the blocks in a second refresh cycle, which is longer than the first refresh cycle, when the semiconductor device is in an externally inaccessible state.
(2) A second aspect of the present invention provides a semiconductor device which holds data by refreshing, comprising:
a memory cell array divided into a plurality of blocks, and
a refresh control circuit which refreshes a block other than a block to be externally accessed among the plurality of blocks of the memory cell array in a first refresh cycle when the semiconductor device is in an externally accessible state, and also refreshes each of the blocks in a second refresh cycle which is longer than the first refresh cycle when the semiconductor device is in an externally inaccessible state.
(3) A third aspect of the present invention provides a memory system comprising the semiconductor device as defined in the above (2).
(4) A fourth aspect of the present invention provides an electronic instrument comprising the semiconductor device as defined in the above (2).